The present invention relates to a semiconductor circuits, and more particularly concerns a chip layout for preventing certain fabrication defects from escaping detection in emitter-couple logic circuits.
Emitter-coupled logic (ECL) is a very high-speed form of logic employing bipolar transistors. An ECL circuit typically employs a function stage for performing a logic function of one or more inputs, and also has an output stage in the form of an emitter follower for driving succeeding ECL circuits. The circuit output is taken across a resistor connected to the emitter of the output transistor and ground. If this resistor is open-circuited due to a fabrication fault in the chip containing the circuit, the circuit will still operate, but at a reduced speed. ECL circuits are commonly tested at a speed which is very low in comparison with its operating speed. This "DC" testing therefore will not detect such a failure.
AC testing--i.e., testing at full operating speed--would detect this type of failure, but such testing is very expensive. With a typical circuit delay of 0.5 nsec or less, such circuits would require microwave techniques in the test equipment and in jigs and fixtures for full testing. One technique for avoiding AC testing of ECL circuits is the use of double contacts at certain points in the circuits. This approach decreases circuit density and still does not provide absolute testability, especially since contacts near each other are more likely to fail together. U.S. Pat. Nos. 4,517,476 (Barre) and 4,410,816 (Kanni), and 28 IBM Technical Disclosure Bulletin 1746-47 (Beh) show other techniques to detect such failures; all of these, however, add additional components to the circuit. Such additional components decrease the overall circuit density and add cost to the fabrication process.